Tuesday, 3 October 2017

Understanding MOSFET Transistor

This article explains about MOSFET which is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. It belongs to a special class of transistor family called Field Effect Transistor (FET). MOSFET is just a type of transistor in FET family of transistors. We will start with some basic terminologies and slowly build up the MOSFET structure.

To understand the operation of MOSFET, we need to understand the terminology – “Field Effect”. Unlike BJT where base current is used to control the flow of electrons from the Emitter to Collector, in Field Effect Transistor, “Electric Field” is used to control the flow. The below diagram explains the difference.
Now, to understand how to use Electric field to control the Electron flow, we need to understand the operation of a simple capacitor. In a simple capacitor, if one side is positively charged, the other is negatively charged. The same principle is used in a MOSFET. The Metal-Oxide-Semiconductor forms a simple capacitor called as MOS capacitor. The structure of the MOS capacitor in a MOSFET is given below.

Now if the Drain and Source are connected to positive and negative potential respectively, the MOS capacitor will be able to control the current flow from Source to Drain. In a symmetric device, the same happens if the Drain and source potential are interchanged. So, the effect by the Electric field of MOS capacitor controls the current flow. Thus, the name “MOS-FET”. 

Let’s consider an NMOS. The structure and symbol of an N-MOSFET fabricated in an IC is shown below:

There are 4 terminals – Gate(G), Drain (D), Bulk (B) and Source (S) in any MOSFET. To be simple, in a MOSFET, the Gate voltage controls the current flow between the Source and the Drain terminals. To turn on the N-MOSFET, we need to first form a pathway (called as channel) for the current flow. In N-MOSFET, generally the current flow is the electrons flowing from Source to Drain since there are plenty of electrons in n-doped regions (at Source and Drain). So, we need a pathway such that electrons in the n-doped region of Source can reach the n-doped region of the Drain. This pathway or channel is formed by applying the voltage at the Gate terminal since Gate terminal is directly above the substrate. The polycrystalline is a conductive layer. The oxide layer, in general is an Insulator. So, (Polycrystalline +Oxide layer + p-substrate) forms a Capacitor.

So, if we apply a positive potential at the Gate, potential becomes negative at the Substrate beneath the oxide. Now we have p-substrate and a negative potential which leads to the recombination of electrons and holes at the oxide-substrate interface (the same action which takes place in a PN Junction diode). So, as the Gate potential continues to rise, depletion region begins to form at the oxide-substrate interface. As the Gate potential is further increased to some extent called Threshold Voltage, some electrons from the depletion layer gets pulled up at the substrate-oxide layer interface and these are mobile electrons. Thus, a channel is formed exactly when Gate Voltage Equals Threshold Voltage. Since the channel is ready, we can apply a potential difference at the Source (-) and Drain (+) to have an electron flow from Source to Drain. Since the direction of conventional current is from + to -, we say that the current flows from Drain to Source and the direction of the current is indicated in the Symbolical representation of the N-MOSFET. 

Symbolically, N-MOSFET is given as:

Or in some text books it could also be given as:

The above symbol is like a conventional bipolar NPN transistor and the direction of arrow indicates the direction of current. This symbol indicates that the Bulk terminal is shorted to the Source terminal.

Sunday, 22 November 2015


In this Article, I am going to explain a basic overview of what a Stored Program concept is and how to realize it. This will be helpful in the study of larger computing blocks and microprocessor systems like 8085/8086. Stored Program Concept is one of the fundamentals that should be known before the study of Microprocessors.

A Stored Program Computer consists of:
- Computing Unit
- Memory
- Bus
- Decoder
- Control Circuitry

Computing Unit:
A Computing Unit is basically to compute certain data. It does not contain full-fledged memory to store more data. But it has less memory to hold at least the operands for the operation being carried out. For example, Calculator contains a “Computing Unit” inside it to compute various operations – Normally the computing unit will be a Microprocessor but to discuss Stored Program Concept, we assume Computing Unit as a black box which can perform operations and give a result.
Computing Unit
Computing Unit
Memory consists of a set of circuitry to store data. The circuitry can be very simple as Invertors connected back to back or using Flip Flops. This is shown diagrammatically below with working explained:
Storing 1 bit data using NOT gates
Storing 1 bit data using NOT gates
In the above construction of the NOT gates, the data given to the NOT gate G1 via the Buffer is given to NOT gate G2 and the output is looped back to G1 again thus maintaining the same value. For example, if we give an input data ‘1’ through the Input Buffer, the data ‘1’ goes through G1 (A1=’1’), then the output of G1 becomes ‘0’ (B1=’0’). Now it goes again to the input of G2 as ‘0’ (A2=‘0’) where the output is ‘1’ (B2=’1’) which is fed to the input of G1 again (A=’1’) and it goes on continues as a loop – thereby storing 1 bit of data. 

The Buffer here is an important gate to learn. It has three states of output. The Buffer is a logic gate unusual to the others, can have three states for output. The behavior of a Buffer is like when the control Bit (in this case ‘C’) is 0, it does not allow any data to flow from INPUT to IN. When the control Bit (‘C’) is 1, it allows the flow of data from INPUT to IN.  The Buffer is used most common in all Microprocessor design and bus architectures.

The Input and Output Buffers are added for the data to be locked inside the NOT gates. The direction of the buffer indicates the direction of the data flow. The Input and Output Buffer’s control bit is complementary to avoid two Input and Output at the same time.

The above is just a simple logic construction which can store 1 Bit of data. This can be considered as a block and can be implemented many times to store multiple bits / bytes of data. Memory is always constructed using Digital Logic and the memory implementation using Flip Flops is shown here.


Bus is nothing but a carrier of signals (data) from one point to another. This is just a set of wires and the direction of which the data should go is controlled by a certain digital logic at the end of the bus. That digital logic which controls the flow of data is again the Buffer. Consider a simple wire shown below where we want to have a data flow from A to B. Now when the control bit C is ‘1’ the data flows from A to B and the direction is always from A to B. When the control bit is ‘0’ whatever the data is from A, it does not flow to B. It is almost like A and B are not connected and behave independent – this is called the ‘High Impedance’ State and is denoted by ‘Z’ at the output. The collection of such wires form a Bus.

The internal implementation of this basic Buffer circuitry (using transistors and diodes) will be described in the next article. 

The Decoder is a logic unit which converts a small set of bits to a larger set of bits. The construction and working of a simple 1:2 decoder is given below:
If it just takes in ‘0’, it gives 01. If it takes in ‘1’, it gives 10. This is too simple to be realized as an application. Let us take a 3 input decoder which can produce (2 to the power 3) – 8 outputs for a single 3 bit input.

If we see the output, it’s 8 Bit which can be used in many practical applications – for example in Memory address decoding. Let us consider a block of memory array shown below from which we need to select one Byte. Practically, the memory layout is different, however the basics of operation is same. Here if we give an input as ‘01’ as i0,i1 – which goes into the decoder – Output as 0010 which selects the correct memory row – which means that it will activate the Output Buffer of each memory unit (we have discussed earlier about the output buffer in each memory unit). Since output buffer is selected, the data flows from memory unit to the output bus. Hence corresponding data selected by the row (highlighted in Yellow) propagates to the output. 

Thus 2 input decoder can address up to 2^2=4 locations. Similarly, 32 bit address lines can address up to 2^32 = 4 GB of memory – they are most commonly referred x86 and 64 bit address lines can address up to more than 1TB of memory – they are referred as x64.

Timing and Control Block:
This block is responsible for generating control signals – basically it ensures on how the data should flow between different units and how each unit is selected so that the operation on the data is done. To realize it we can think of it as a Decoder – which can decode an Instruction to a set of control signals - Instruction Decoder – which can be used to send to control signals to various blocks inside the computing unit. Let us take an Example to see exactly how it works:

We are performing an addition operation. Assuming we had already loaded the operands from the memory to the computing unit, we have to tell the computing unit to perform a multiplication operation. This is how it is performed – We say the computing unit to “ADD” which is hard coded internally to be an n-bit number which is called as the OPCODE for an instruction – can be found in datasheet/reference of a microprocessor. So, this n-bit number goes to the input of the decoder and the output of the decoder may be like (010010011). Here this set of Bits is used to ‘on’ or ‘off’ certain parts of the computing unit. In this example, this set of bits will help switch on the ADD unit (the addition logic block – which may be implemented using n-bit full adder circuit). So, if we would have given an instruction like MUL – the Instruction decoder might have given the output as (01110010) a different pattern to enable the Multiplication block (which may be implanted using Multiplier Logic circuit). So, it is simple. Each Instruction -> Specific control bits for performing that specific operation.

Now to the stored program computer concept. We have seen all the basics above. Now we will be integrating them so that the system can run a program from a memory. For example we store a basic addition program in the memory – which needs to be executed. It is realized as:

Internally, Stored Program Computer is specified as:

Stored Program Computer

The Memory is expanded to provide a clear picture:
Memory Addressing
Memory Addressing

We see that the program for addition of two numbers is stored at 00 80 H. To start the program execution, we load the program counter with 00 80 H – this value goes via the Address Bus to the Memory decoder – pulls in the code B0 05 – a MOV instruction – which goes into the timing and control unit such that it loads the data 05 H to the Internal temporary register AL in the computing unit. Thus bringing the operands to the internal temporary registers of the computing unit. (Consider AL and BL as temporary registers inside the computing unit). Then after executing the first code at 00 80 H, the program counter increments automatically and becomes 0082H (Consider increment by 2 since the instruction size is 2 bytes) and executes the next MOV instruction which brings the next operand to BL. Now program counter increments to 00 84 H to bring it the ADD instruction -> which performs the Addition of the data. Thus a simple addition program is executed successfully. 

We have seen how a simple program is executed in a computing unit – which forms the basics of a Microprocessor. Most of the construction that we discussed in the above article may not come up in the practical implementation but the concepts discussed above will prevail and will definitely be a building block for learning a Microprocessor Architecture.